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AR# 58981

7 Series GTP Transceivers - TX and RX Latency Values

Description

This answer record provides the TX and RX latency values for the 7 series FPGA GTP Transceiver. The tables will be added to the 7 Series FPGAs GTP Transceivers User Guide (UG482).

Solution

Notes:

  1. RXDDIEN must be 1 to ensure predictable fixed latency when using RX buffer bypass.
  2. The minimum and maximum are theoretical. These configurations may not map to any protocol.
  3. USRCLK and USRCLK2 phases are assumed to be matching according to the user guide.
  4. The latency through the TX fabric interface will depend on one's precise definition of latency; the entries in the above table are accurate if latency is defined as the time from the clock edge that puts data on TXDATA to the clock edge that clocks the first part of that data out of the fabric interface (into the internal PCS), neglecting clock insertion time from the fabric into the GT.
AR# 58981
Date Created 01/02/2014
Last Updated 01/06/2014
Status Active
Type General Article
Devices
  • Artix-7
  • Artix-7Q
  • Zynq-7000
  • More
  • XA Zynq-7000
  • Zynq-7000Q
  • Less