The maximum SCL clock frequency in Standard Mode is specified as 100 kHz with a minimum tHD; STA timing of 4.0 microseconds.
The Zynq I2C controller timing for tHD; STA is as follows:
- At 100 kHz, the controller provides 3.6 us.
- At 90 kHz, the controller provides 4.0 us.
- Below 90 kHz, the controller exceeds 4.0 us.
Note: This issue only applies to I2C Standard Mode (not Fast Mode).
Note: The SCL clock frequency and tHD; STA timing depend on the APB bus clock frequency, CPU_1x, and the divider values in the i2c.Control_reg0 register.
All of the latest I2C devices support Fast Mode which has a maximum SCL clock frequency of 400 kHz and a minimum tHD; STA of 0.6 us.
This timing can be achieved by the controller and is not affected by this issue.
For Standard Mode applications, 90 kHz should be acceptable in most situations.
There are 3 work-arounds:
- For standard mode, run the interface at or below 90 kHz.
- For standard mode, tHD;STA of 3.6 us may be acceptable at 100 kHz.
- Use Fast mode.
Systems that use the I2C in Standard Mode.
Device Revision(s) Affected:
All, No plan to fix.
Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences