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AR# 59383

VC7222 IBERT - UG971 Example Design Creates Erroneous Period Constraints


There is a known issue with the clocking constraints generated by the VC7222 IBERT example design.

This issue only appears on Windows machines, and it stems from a problem in the Windows TCL libraries. Period constraints for each line rate will be generated incorrecty, many of them will be negative.


To avoid this issue, generate the design on a Linux machine. If this is not possible, then the problematic period constraints will need to be fixed by hand.

Following is an example of the incorrect (generated) and correct (manually edited) constraints for the 28.5Gb/s line rate:

Constraint File: ibert_7series_gtz.xdc

Erroneous Line 37: set_property CLKIN1_PERIOD -79.413 [get_cells u_ibert/inst/OCT1.u_oct1/gearbox0/mmcm_adv_inst]
Corrected Line 37: set_property CLKIN1_PERIOD   5.704 [get_cells u_ibert/inst/OCT1.u_oct1/gearbox0/mmcm_adv_inst]

Erroneous Line 42: set_property CLKIN1_PERIOD -79.413 [get_cells u_ibert/inst/OCT1.u_oct1/gearbox1/mmcm_adv_inst]
Corrected Line 42: set_property CLKIN1_PERIOD   5.704 [get_cells u_ibert/inst/OCT1.u_oct1/gearbox1/mmcm_adv_inst]

Constraint File: timing.xdc

Erroneous lines 6 thru 11:
create_clock -period -79.413 -name GTZ_RXCLK0_1 [get_pins {u_ibert/inst/OCT1.u_oct1/clkbuflbrx0/O}]
create_clock -period -79.413 -name GTZ_RXCLK1_1 [get_pins {u_ibert/inst/OCT1.u_oct1/clkbuflbrx2/O}]
create_clock -period -79.413 -name GTZ_RXUCLK1_1 [get_pins {u_ibert/inst/OCT1.u_oct1/gearbox0/mmcm_out/O}]
create_clock -period -79.413 -name GTZ_RXUCLK3_1 [get_pins {u_ibert/inst/OCT1.u_oct1/gearbox1/mmcm_out/O}]
create_clock -period -79.413 -name GTZ_TXCLK0_1 [get_pins {u_ibert/inst/OCT1.u_oct1/gtze2_inf_north/clkbuflbtx0/CLKOUT}]
create_clock -period -79.413 -name GTZ_TXCLK1_1 [get_pins {u_ibert/inst/OCT1.u_oct1/gtze2_inf_north/clkbuflbtx1/CLKOUT}]

Corrected lines 6 thru 11:
create_clock -period 5.704 -name GTZ_RXCLK0_1 [get_pins {u_ibert/inst/OCT1.u_oct1/clkbuflbrx0/O}]
create_clock -period 5.704 -name GTZ_RXCLK1_1 [get_pins {u_ibert/inst/OCT1.u_oct1/clkbuflbrx2/O}]
create_clock -period 5.704 -name GTZ_RXUCLK1_1 [get_pins {u_ibert/inst/OCT1.u_oct1/gearbox0/mmcm_out/O}]
create_clock -period 5.704 -name GTZ_RXUCLK3_1 [get_pins {u_ibert/inst/OCT1.u_oct1/gearbox1/mmcm_out/O}]
create_clock -period 5.704 -name GTZ_TXCLK0_1 [get_pins {u_ibert/inst/OCT1.u_oct1/gtze2_inf_north/clkbuflbtx0/CLKOUT}]
create_clock -period 5.704 -name GTZ_TXCLK1_1 [get_pins {u_ibert/inst/OCT1.u_oct1/gtze2_inf_north/clkbuflbtx1/CLKOUT}]
AR# 59383
Date Created 02/10/2015
Last Updated 02/13/2014
Status Active
Type Known Issues
  • Virtex-7
  • Vivado Design Suite - 2013.4