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AR# 59498

2013.4 Vivado HLS - C Synthesis hangs for a long period of time.

Description

In my design there is one large loop under one PIPELINE directive:

LOOP_OUT:for(...){

#pragma HLS PIPELINE II=512

   float sum = 0;
   Loop_IN:for (int id = 0; id < 4096; ++id)
   {
    sum += a[ia][id] * b[id][ib];
   }
   out[ia][ib] = sum;

}

C Synthesis hangs for a long time. 

In Linux, it reports:

@E [HLS-103] Unexpected standard exception occurred: std::bad_alloc.
Synthesis failed.
    while executing
"csynth_design"

Solution

This issue is caused by PIPELINE unrolling all loops under it, no matter what II is. 

Rewrite the code as follows to work around it:

LOOP_OUT:for(...){

            #define UNROLL_FAC 8
            float sum_i[UNROLL_FAC];
            for(int ii=0;ii<UNROLL_FAC;++ii){
                sum_i[ii]=0;
            }
            Loop_IN:for (int id = 0; id < 4096/UNROLL_FAC; ++id)
            {
#pragma HLS PIPELINE
                Loop_IN2:for(int ii=0;ii<UNROLL_FAC;++ii){
                    sum_i[ii] += a[ia][4096/UNROLL_FAC*ii+id] * b[4096/UNROLL_FAC*ii+id][ib];
                }
            }
            for(int ii=0;ii<UNROLL_FAC;++ii){
                out[ia][ib]+=sum_i[ii];
            }
        }

}

AR# 59498
Date Created 02/20/2014
Last Updated 03/11/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.4