During the write_bitstream stage, I receive the following DRC error message:
Why does this DRC violation occurs?
There are cascaded DSP primitives in the design.
These DSPs are connected from the PCOUT pin of the upstream DSP to the PCIN pin of the downstream DSP.
This is the dedicated route, and the DSP should be placed in the adjacent location.
This is a valid DRC error message.
If you receive the error message, check why the cascaded DSPs are not placed in the adjacent location.