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  3. AR# 59901: UltraScale FPGA Gen3 Integrated Block for PCI Express v3.0 - Enabling GT Wizard mode in Vivado

AR# 59901

UltraScale FPGA Gen3 Integrated Block for PCI Express v3.0 - Enabling GT Wizard mode in Vivado

Description

This answer record provides instruction to enable GT Wizard mode for UltraScale FPGA Gen3 Integrated Block for PCI Express v3.0 core in Vivado 2014.1.

The following commands are used to enable GT Wizard mode.

1.    create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name <component_name>
2.    set_property -dict [list CONFIG.dis_gt_wizard {false}] [get_ips <component_name>]

When the variable dis_gt_wizard is set to false then the GT wizard mode will be enabled; when the core is generated, GT Wizard core will be picked up as a subcore.

When the variable dis_gt_wizard is set to true then the GT channel blocks will be delivered as a part of the UltraScale FPGA Gen3 Integrated Block for PCI Express core.

Solution

Please follow the steps below to enable the GT wizard mode. This is disabled by default (dis_gt_wizard is set to true).

Step:1
Create a project in 2014.1 Vivado for an Ultrascale device and click on the IP catalog. It should list UltraScale FPGA Gen3 Integrated Block for PCI Express core.

Step:2
In the tcl console, type the following command.
create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0

Step:3
After the command in Step-2, enter the following command.
set_property -dict [list CONFIG.dis_gt_wizard {false}] [get_ips pcie3_ultrascale_0]

Step:4
Once the parameter is set to false, right click on the xci file in the Sources panel and then select Generate Output Products.

You should see pcie3_ultrascale_0_gt listed under "Sub-cores" when you expand pcie3_ultrascale_0 tree in 'IP Sources' Tab in 'Sources' window.

Note: If any other parameter needs to be customized, just double click on the xci file which opens up the customization GUI.

When all required parameters are set then click ok to generate the core again.

Revision History:
04/02/2014 - Initial Release
AR# 59901
Date 04/16/2014
Status Active
Type General Article
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)

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