We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 59963

Zynq-7000 SoC - PS DDRC LPDDR2 Controller Instability in Xilinx tools before 2014.1


I am seeing memory errors when using LPDDR2 via the Zynq-7000 PS DDRC controller. 

How do I resolve this issue?


There are multiple LPDDR2-related memory parameters that are not correctly generated in  ps7_init.c and ps7_init.tcl from the user Vivado/XPS GUI selections. 

These include:

  • reg_ddrc_t_cke
  • reg_ddrc_wr2rd
  • reg_ddrc_write_latency
  • reg_ddrc_t_rcd
  • reg_ddrc_emr (write latency)

This issue is fixed in Vivado release 2014.1.


A patch is available for ISE/EDK 14.7 in (Xilinx Answer 60454)

A ps7_init.tcl/.c from 2014.1 can be used for earlier Vivado versions.
AR# 59963
Date Created 03/26/2014
Last Updated 05/26/2014
Status Active
Type General Article
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q