This timing warning is not significant, and can be safely ignored.
Instead, timing analysis should be performed post implementation to verify the design meets timing.
An example warning message is below:
TIMING-17#1 WarningThis is a tool issue relating to the VIO core, currently no fix is planned.
Non-clocked sequential cell
The clock pin example_hid/example_vio/inst/DECODER_INST/Bus_data_out_reg[*]/C is not reached by a timing clock
Related violations: <none>