When using the AXI4 Interface on the clock wizard the Locked status can be incorrectly set.
This is a known issue and will be resolved in Vivado 2014.2.
The following is the workaround for Vivado 2014.1 Clocking wizard v5.1:
This issue is due to the decoding logic for the status signal in the <core_name>_clk_wiz_drp.vhd file.
In the above code snippet 100000 is incorrect, 101000 should be used instead.
The Workaround for this issue is to read base_address + 0x0 register bit  instead of reading base_address + 0x4 register bit