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AR# 60568

Clock Wizard v5.1 - Vivado 2014.1 - Locked status not set correctly on Clock wizard IP when doing Dynamic reconfiguration via an AXI4lite interface


When using the AXI4 Interface on the clock wizard the Locked status can be incorrectly set.


This is a known issue and will be resolved in Vivado 2014.2.

The following is the workaround for Vivado 2014.1 Clocking wizard v5.1:

This issue is due to the decoding logic for the status signal in the <core_name>_clk_wiz_drp.vhd file.

case register_rdce_select is
-- bus2ip_rdce(1,2,8)
when "001000" =>
IP2Bus_Data <= ram_clk_config(conv_integer(ram_addr));
when "100000" =>
IP2Bus_Data(30 to 31) <= program_status;
IP2Bus_Data(0 to 29) <= (others => '0');

In the above code snippet 100000 is incorrect, 101000 should be used instead.

The Workaround for this issue is to read base_address + 0x0 register bit [1] instead of reading base_address + 0x4 register bit [0]

AR# 60568
Date Created 05/08/2014
Last Updated 05/27/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.1