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AR# 61099

JESD204B - v5.1 - Timing Failures seen in JESD204 Example Design Operating on -1 Devices above 6.5 GHz

Description

When running the JESD204 example design above 6.5GHz (reference clock > 165 MHz) on a Kintex-7, Zynq or Virxtex-7 -1 device, a second clock input is required in the example design and support layer block to drive the JESD204 core clock, due to limitations on sampling SYSREF.

Currently, the default example design for -1 devices uses a single clock (refclk) to drive both transceiver and JESD204 core.

This is seen in JESD204 versions 4.0 to 5.2.

Solution

To allow us to modify the JESD204 files, the core must be generated with the Support Logic in the Example Design.

The following steps will add the required ports to the Support Level Block, and make the required modifications to the Clocking Module located in the Support Level Block. 


Note: Steps 4-6 are only required when attempting to run simulations using the default test bench provided with the JESD204 example design above 6.5GHz.

They are required for the default JESD204 example design on Virtex-7 -1 GTH Devices which run at 8 GHz by default.


1. Open a new Vivado project and select the same device using a -2 speed grade.


2. Create a new JESD204 core using the same name as was used in the initial project, but include the Shared Logic in Core (If you will be running simulations above 6.5GHz, open the example design to generate the example design top level and demo test bench.).


3. Once the core has been generated, replace the following files  in the initial project located at initial_project_directory/<core_name>_example/<core_name>_example.srcs/sources_1/imports/example_design/support/ with those located at dash2_project_directory/<project_name>.srcs/ip/<core_name>/synth/:

  • <core_name>_support.v
  • <core_name>_clocking.v


4. Locate the file initial_project_directory /<core_name>_example/<core_name>_example.srcs/ sources_1/imports/example_design/<core_name>example_design.v, and replace it with dash2_project_directory /<core_name>_example/<core_name>_example.srcs/ sources_1/imports/example_design/<core_name>example_design.v.

This  will replace the top level of the example design.


5. Open the <core_name>_example_design.xdc in the initial project and add the following constraint to create the new clock added above:

create_clock -period <period_value> name glblclk [get_ports glblclkp]


6. The demo testbench must now be replaced to include the new clock inputs.

This can be done by replacing the file located at initial_project_directory/<core_name>_example/<core_name>_example.srcs/sim_1/imports/ <core_name>/simulation/demo_tb.v with dash2_project_directory/<core_name>_example/<core_name>_example.srcs/sim_1/imports/ <core_name>/simulation/demo_tb.v


Revision History:

Initial Release: 06/11/14

AR# 61099
Date Created 06/11/2014
Last Updated 10/14/2015
Status Active
Type General Article
IP
  • JESD204