UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61402

7 Series Integrated Block for PCI Express v3.0 (Rev2) - PCIe x8Gen2 PIO example design for k70tfbg676-2 device fails in timing

Description

Version Found: v3.0 (Rev2)
Version Resolved and other Known Issues: See (Xilinx Answer 54643)

When generating the x8Gen2  7-Series Integrated Block for PCI Express v3.0 (Rev2) core for an xc7k70tfbg676-2 device, the PIO example design fails in timing.

Solution

To work around this issue, enable pipelining registers by setting the following parameters to '1' in the pcie_7x_0_core_top.v file:

  • TL_RX_RAM_WRITE_LATENCY
  • TL_TX_RAM_WRITE_LATENCY
  • TL_RX_RAM_RADDR_LATENCY
  • TL_TX_RAM_RADDR_LATENCY

This will be fixed in a future release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
07/07/2014 - Initial Release 

Linked Answer Records

Master Answer Records

AR# 61402
Date Created 07/07/2014
Last Updated 07/08/2014
Status Active
Type Known Issues
IP
  • 7 Series Integrated Block for PCI Express (PCIe)