Version Found: v3.0 (Rev2)
Version Resolved and other Known Issues: See (Xilinx Answer 54643)
When generating the x8Gen2 7-Series Integrated Block for PCI Express v3.0 (Rev2) core for an xc7k70tfbg676-2 device, the PIO example design fails in timing.
To work around this issue, enable pipelining registers by setting the following parameters to '1' in the pcie_7x_0_core_top.v file:
This will be fixed in a future release of the core.
Note: "Version Found" refers to the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
07/07/2014 - Initial Release