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AR# 61423

Vivado - Hold violation occurs for a path starting from BUFG/O

Description

A path starting from a clock buffers output pin and ending at a registers D input pin shows hold violations:

 

Min Delay Paths

--------------------------------------------------------------------------------------

Slack (VIOLATED) :        -0.745ns  (arrival time - required time)

  Source:                 ccu/clkout0_buf/O

                            (clock source 'core_clock'  {rise@0.000ns fall@15.000ns period=30.000ns})

  Destination:            I25_core/nic0/ac/atc/atc_miss_buffer/atc_miss_buf_bank/DPRAM/memory.atc.atc_miss_buffer.atc_missbuf_ctrl.mb_arb_req_packet_r0_ret[4]/D

                            (rising edge-triggered cell FDRE clocked by core_clock  {rise@0.000ns fall@15.000ns period=30.000ns})

  Path Group:             core_clock

  Path Type:              Hold (Min at Slow Process Corner)

  Requirement:            0.000ns  (core_clock rise@0.000ns - core_clock rise@0.000ns)

  Data Path Delay:        2.192ns  (logic 0.036ns (1.643%)  route 2.156ns (98.357%))

  Logic Levels:           1  (LUT5=1)

  Clock Path Skew:        2.367ns (DCD - SCD - CPR)

    Destination Clock Delay (DCD):    2.367ns

    Source Clock Delay      (SCD):    0.000ns

    Clock Pessimism Removal (CPR):    -0.000ns

  Clock Uncertainty:      0.087ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE

    Total System Jitter     (TSJ):    0.071ns

    Discrete Jitter          (DJ):    0.159ns

    Phase Error              (PE):    0.000ns

  Inter-SLR Compensation: 0.329ns  (DPD * PF)

    Data Path Delay         (DPD):    2.192ns

    Prorating Factor         (PF):    0.150

 

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)

  -------------------------------------------------------------------    -------------------

                         (clock core_clock rise edge)

                                                      0.000     0.000 r 

    BUFGCTRL_X0Y33       BUFG                         0.000     0.000 r  ccu/clkout0_buf/O

                         net (fo=525149, routed)      2.156     2.156    I25_core/nic0/ac/atc/atc_miss_buffer/atc_miss_buf_bank/DPRAM/clk

    SLR Crossing[1->3]

    SLICE_X451Y505       LUT5 (Prop_lut5_I4_O)        0.036     2.192 r  I25_core/nic0/ac/atc/atc_miss_buffer/atc_miss_buf_bank/DPRAM/memory.atc.atc_miss_buffer.atc_missbuf_ctrl.mb_arb_req_packet_r0_3[4]/O

                         net (fo=1, routed)           0.000     2.192    I25_core/nic0/ac/atc/atc_miss_buffer/atc_miss_buf_bank/DPRAM/mb_arb_req_packet_r0_3[4]

    SLICE_X451Y505       FDRE                                         r  I25_core/nic0/ac/atc/atc_miss_buffer/atc_miss_buf_bank/DPRAM/memory.atc.atc_miss_buffer.atc_missbuf_ctrl.mb_arb_req_packet_r0_ret[4]/D

  -------------------------------------------------------------------    -------------------

 

                         (clock core_clock rise edge)

                                                      0.000     0.000 r 

    BUFGCTRL_X0Y33       BUFG                         0.000     0.000 r  ccu/clkout0_buf/O

                         net (fo=525149, routed)      2.367     2.367    I25_core/nic0/ac/atc/atc_miss_buffer/atc_miss_buf_bank/DPRAM/clk

    SLR Crossing[1->3]

    SLICE_X451Y505                                                    r  I25_core/nic0/ac/atc/atc_miss_buffer/atc_miss_buf_bank/DPRAM/memory.atc.atc_miss_buffer.atc_missbuf_ctrl.mb_arb_req_packet_r0_ret[4]/C

                         clock pessimism              0.000     2.367   

                         inter-SLR compensation       0.329     2.696   

                         clock uncertainty            0.087     2.783   

    SLICE_X451Y505       FDRE (Hold_fdre_C_D)         0.154     2.937    I25_core/nic0/ac/atc/atc_miss_buffer/atc_miss_buf_bank/DPRAM/memory.atc.atc_miss_buffer.atc_missbuf_ctrl.mb_arb_req_packet_r0_ret[4]

  -------------------------------------------------------------------

                         required time                         -2.937   

                         arrival time                           2.192   

  -------------------------------------------------------------------

                         slack                                 -0.745    


Solution

From the path details, you can see that the clock buffer's output is reaching the D pin of FF.

This timing scenario is called clock used as data.

This topology is usually not recommended as timing closure on such paths can be tricky.

What is most likely happening in this case is that the router starts by routing the clock nets, including the segments ending to non-clock pins, and does not revisit these routes later on, even to fix timing violation.

Because the LUT5 is placed directly in front of FD/D, the net between LUT/O and FD/D cannot be detoured to fix hold.

Hold cannot be fixed with this placement.

If the LUT is placed in a different slice, it should be ok.
 

If there is no valid reason for this path to exist or to meet timing in order to be functional, then the following constraint will get rid of it while maintaining the default period constraint on all clock pins in the fanout of the BUFG:

set_false_path -through [get_pins bufg_inst/O]

AR# 61423
Date Created 07/08/2014
Last Updated 03/06/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite