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AR# 61665

Zynq-7000 AP SoC, I2C - Missing I2C Master Completion Interrupt

Description

The I2C controller when configured in Master Mode is the missing master completion interrupt.

Solution

 

Description:  

When the I2C Controller is operating as a master, a completion interrupt should be signaled when a transfer is complete. 

This interrupt is not signaled after a transfer if the transfer was initiated with a repeated start condition.

The exact sequence is as follows:

  1. Master begins a read transfer.
    a.    This transfer could begin with a Start or a Repeated Start condition.
    b.   The HOLD bit (i2c.Control_reg0[HOLD]) must be set at the end of the transfer.
    c.    The COMP interrupt (i2c.Interrupt_status_reg0[COMP]) will be properly signaled when this transfer is done.

  2. Master begins a second read transfer with a new address.
    a.    Because the HOLD bit was set in step1, the controller will begin this transfer with a repeated start condition.
    b.   The HOLD bit must be cleared at the end of the transfer. This will cause a STOP condition.
    c.    The COMP interrupt will not be signaled when this transfer is done.


Impact

Major. Software will not be able to process the transfer until the interrupt happens.

However since the interrupt never comes, the outstanding transfer may not get processed correctly.


Work-around

Do not use repeated start for back to back read transfers. 

Alternatively, the driver can poll the i2c.Transfer_size_reg0 register when it is less than 14B to keep track of the end of the transfer.

       

Configurations Affected: Systems that utilize I2C as a master.

Resolution:  No Fix Planned

Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.

 

AR# 61665
Date Created 07/31/2014
Last Updated 08/25/2014
Status Active
Type Design Advisory