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AR# 61911

LogiCORE IP JESD204 PHY core - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP JESD204 PHY core and includes the following:

 

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.3 and newer tools.

For Known Issues with the LogiCORE IP JESD 204 core, please visit

(Xilinx Answer 44405) LogiCORE IP JESD204 - Release Notes and Known Issues


Or

(Xilinx Answer 54480) LogiCORE IPJESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools.

 

 

LogiCORE IP JESD204 core IP Page:

http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-jesd204.html

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Alternatively, see the Change Log Answer Records:

 

Answer Record Title
(Xilinx Answer 67345) 2016.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 66930) 2016.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 66004) 2015.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 65570) 2015.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 65077) 2015.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 64619) 2015.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 63724) 2014.4.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 62882) 2014.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 62144) 2014.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 61087) 2014.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 59986) 2014.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 58670) 2013.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 58605) 2013.3 Vivado IP Release Notes - All IP Change Log Information

 

For any Transceiver related questions or issue, please see the table below.

 

Answer Record Title
(Xilinx Answer 41613) 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List
(Xilinx Answer 57487) UltraScale FPGA Transceiver Wizard - Release Notes and Known Issues for Vivado 2013.4 and newer versions
(Xilinx Answer 62670) UltraScale FPGAs GTH Transceiver - Known Issues and Answer Record List
(Xilinx Answer 64440) UltraScale FPGA GTY Transceiver - Known Issues and Answer Record List
(Xilinx Answer 64838) Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates in Vivado 2015.2

 

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

 

Core Version Vivado Tools Version
v3.2 2016.3
v3.1 (Rev. 1) 2016.2
v3.1 2016.1
v3.0 2015.4
v2.0(Rev. 2) 2015.3
v2.0 (Rev. 1) 2015.2
v2.0 2015.1
v1.0 (Rev. 2) 2014.4.1
v1.0 (Rev. 1) 2014.4
v1.0 2014.3




Known and Resolved Issues

The following table provides known issues for the LogiCORE IP JESD204 PHY core, starting with v1.0, initially released in Vivado 2014.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

 

Answer Record Title Version Found Version Resolved
(Xilinx Answer 63634) LogiCORE IP JESD204 PHY v1.0 - TX_RESET_GT and RX_RESET_GT affect both TX and RX SERDES v1.0 v2.0
(Xilinx Answer 64749) LogiCORE IP JESD204 PHY v2.0 - CPLLPD not correctly set v2.0 v2.0 (Rev. 1)
(Xilinx Answer 65313) LogiCORE IP JESD204 PHY v2.0 - MMCM_Locked output port not generated for JESD PHY core generated with Shared Logic in Core option  v2.0 v3.0
(Xilinx Answer 66029) LogiCORE IP JESD204 PHY v3.0 - Core fails to generate UltraScale Transceiver with correct settings for some configurations v3.0  
(Xilinx Answer 66575) JESD204 and JESD204 PHY - Multi-lane JESD interfaces and the rxencommaalign signal    
(Xilinx Answer 66576) JESD204 - Clock stability    
(Xilinx Answer 67043) JESD204 v7.0 and JESD204_PHY v3.1 - 2016.1 - Defaults to DFE Equalisation mode    
(Xilinx Answer 67044) JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - TXDIFFCTRL low default value    
(Xilinx Answer 67354) JESD204 PHY - CPLLPD is not held high for at least 2us   v3.2

 

Revision History

 

25/11/2016 Added (Xilinx Answer 67354)
06/10/2016 Added (Xilinx Answer 67345)
05/11/2016 Added (Xilinx Answer 67043)(Xilinx Answer 67044), (Xilinx Answer 66930)
02/09/2016 Added (Xilinx Answer 66576)
02/09/2016 Added (Xilinx Answer 66575)
12/10/2015 Added (Xilinx Answer 66004)
11/26/2015 Added (Xilinx Answer 66029)
09/01/2015 Added (Xilinx Answer 65313)
08/28/2015 Updated for 2015.2 release. Added (Xilinx Answer 65077).
07/03/2015 Added (Xilinx Answer 64838)
06/12/2015 Added (Xilinx Answer 64749)
06/04/2015 Updated for 2015.1 release. Added (Xilinx Answer 62670) and (Xilinx Answer 64440)
02/19/2014 Added (Xilinx Answer 636340)
01/20/2014 Updated for 2014.4 release
10/07/2014 Initial Release

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
64838 Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates in Vivado 2015.2 N/A N/A
AR# 61911
Date Created 09/03/2014
Last Updated 11/25/2016
Status Active
Type Release Notes
IP
  • JESD204