On the VCU108 evaluation kit, due to the revision implementation, a configuration failure (DONE will not go high) will be seen if the default bitstream options are used.
To prevent a master BPI configuration failure in Asynchronous read, the VU095 FPGA bitstream image MUST be compressed.
See the Solution section for the proper compression constraint syntax to use.
The VCU108 Evaluation Kit address pin connections between the Virtex UltraScale FPGA (VU095) and the Micron (PC28F00AG18FE) Flash are as follows:
The RS[0:1] pins effectively divide the flash into 4 sections based on the upper flash address pin setting (RS=00, RS=01, RS=10, and RS=11) allowing for easy revision selection with a dip switch.
The VCU108 RS[0:1] are pulled up or pulled down dependent on the on-board dip switch setting.
Once the RS pin selection is set, the configuration is started from one of the four image locations targeted by the switch setting.
Because the flash is effectively split into 4 sections by the RS pin implementation, the bitstream must be smaller than a quarter of the flash density.
The VCU108 Evaluation Kit has a 1Gb Micron flash and the VU095 FPGA bitstream slightly passes the quarter flash boundary (268,435,456 bits) by <7%.
When a bitstream running with the Master BPI Configuration Asynchronous read mode is greater than the next quarter flash boundary, it will wrap due to the RS static settings and not see the end of the bitstream.
Compression MUST be used when using the Master BPI Configuration Asynchronous read or a configuration failure will be seen.
Add the following constraint for compression to designs targeted for the VCU108 customer evaluation kit.
If 4 images are not required to be programmed, then the Master BPI Configuration Synchronous read mode is another option.In the Master BPI Configuration mode with Synchronous read the flash bursts data so it does not encounter an issue with the revision boundary (1/4 of the flash).