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AR# 62034

7 Series - 2014.2/2014.3 write_bitstream error - EMCCLK pin must be programmed as an input when generating a bitfile for configuration


The following error is observed when running write_bitstream to generate a bitfile using the External Master Configuration Clock (EMCCLK) for configuration of the 7 Series FPGA with SPI/BPI flash.

ERROR: [Designutils 12-2331] Pin IOB_X0Y143 is the EMCCLK pin and must be programmed as an input when the ExtMasterCclk_en option is not set to Disable.

How can this issue be resolved?


The PACKAGE_PIN constraint should not be used. 

Remove the PACKAGE_PIN constraint below from the XDC file:

set_property PACKAGE_PIN <xxx> [get_ports emcclk]


The following attributes are common settings in the XDC file to allow for the use of EMCCLK.

set_property PACKAGE_PIN <xxx> [get_ports emcclk]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN <div-1|div-2|div-4|div-8> [current_design]
set_property CONFIG_VOLTAGE <3.3|2.5|1.8> [current_design]
set_property CFGBVS <VCCO|GND> [current_design]

This error is observed in 2014.2 and 2014.3 when the PACKAGE_PIN constraint is set in the XDC file.
In 2014.3/2014.2, the front end optimization tools ignore the PACKAGE_PIN constraint and do not create an input buffer when the signal is not used in the design.
It is not necessary to declare the EMCCLK input when the signal is not being used in the design and is only being used for configuration.

This issue will be fixed in the 2014.4 release. 

See (Xilinx Answer 44635) for additional EMCCLK details.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44635 7 Series - EMCCLK considerations to ensure the FPGA completes the startup sequence N/A N/A
AR# 62034
Date Created 09/12/2014
Last Updated 11/04/2014
Status Active
Type General Article
  • Kintex-7
  • Artix-7
  • Virtex-7
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2