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AR# 62254

Zynq BFM simulation - Invalid release of reset.


The following occurs when I use Vivado IP Integrator (IPI) with a Zynq PS or with a Zynq BFM model.

When the simulation is launched, the Zynq PS is swapped for the Zynq BFM simulation model and a simulation design is built using the same connections as on the PS7.




Reset checks happen on ALL AXI ports: enabled or NOT.

AXI ports which are DISABLED fail to pass the check with the following error: (this example assumes M_AXI_GP1 is DISABLED)

M_AXI_GP1 : *ERROR : Invalid release of reset. Reset can be asserted asynchronously but must be deasserted on the rising edge of the clock - AMBA AXI SPEC V2 - Section 11.1.2 Reset

This occurs because all disabled AXI ports clock input are connected (to '0').

This enables the RESET checks.


To minimize corrections, the best way to get around this problem is to present the RESET signal to be active on the DISABLED ports (Active low).
Three files (two files that instantiate the AXI SLAVES BFMs and one file that instantiates the AXI MASTER BFMs) need to be altered to keep the reset input 'high'.
Extract the files in the zip file attached to this Answer Record and place the three files in the Xilinx installation folder:


Associated Attachments

Name File Size File Type
zynq_bfm_in_rst.zip 18 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58884 Xilinx Simulation Solution Center - Design Assistant - IP Simulation N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
62030 ModelSim simulation of Zynq BFM throws error on non zero reset value. N/A N/A
AR# 62254
Date Created 09/29/2014
Last Updated 07/04/2016
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2014.2
  • Processing System 7