The following occurs when I use Vivado IP Integrator (IPI) with a Zynq PS or with a Zynq BFM model.
When the simulation is launched, the Zynq PS is swapped for the Zynq BFM simulation model and a simulation design is built using the same connections as on the PS7.
Reset checks happen on ALL AXI ports: enabled or NOT.
AXI ports which are DISABLED fail to pass the check with the following error: (this example assumes M_AXI_GP1 is DISABLED)
This occurs because all disabled AXI ports clock input are connected (to '0').
This enables the RESET checks.
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