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AR# 62356

7 Series MIG - LPDDR2 - Initialization errors seen in simulation

Description

Version Found: MIG 7 Series v2.1

Version Resolved: See (Xilinx Answer 54025)


When simulating LPDDR2, the following errors might be observed:

ddr_test.b0.ERROR at time            765511000: Nop or Deselect must be driven in the clock cycle after CKE goes low

ddr_test.b0.ERROR at time           1917511000: Nop or Deselect must be driven in the clock cycle after CKE goes low

ddr_test.b0.ERROR at time           4524171000: tINIT3 violation

Solution

These initialization errors are safe to ignore.  

The "Nop or Deselect" errors are due to a simulation glitch where unknown X values are driven on several of the lines during initialization:

 lpddr2.png

 

This causes the memory model to believe that CKE has gone high and then low again, which flags the error. 

The tINIT3 violation is caused by the abbreviated initialization and calibration sequence used during simulation. 

The JEDEC tINIT3 requirement is that the command bus must remain idle (NOP) for at least 200 us after CKE is asserted.  

Because this wait period is skipped during the FAST version of initialization/calibration, the tINIT3 error above is given.

Revision History
10/3/2014 - Initial Release

 

AR# 62356
Date Created 10/03/2014
Last Updated 11/04/2014
Status Active
Type General Article
IP
  • MIG 7 Series