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AR# 62551

MIG UltraScale x4 Devices - Incorrect EN_OTHER_PCLK and EN_OTHER_NCLK parameters generated by MIG


Version Found: MIG v6.0
Version Resolved: See (Xilinx Answer 53485)

The MIG UltraScale designs have EN_OTHER_PCLK and EN_OTHER_NCLK parameters defined in the cores top level (core_name_mig.sv) file.  

The parameters set which of the bytes DQS pins (1 set per nibble) are calibrated with the associated DQ pins.  

For a given byte, there are two nibbles. 

The parameter has a '1' to signify the nibble should be calibrated using the DQS from the other nibble in the given byte. 

For a x8 implementation, the parameter sets 2'b01 for the lower nibble DQ pins to calibrate to the DQS in the upper nibble (nibble 1) and a 2'b00 for the upper nibble DQ pins to calibrate to that same DQS in the upper nibble.  

Because x4 parts each use the DQS allocated in the same nibble as all of the corresponding DQ pins, the parameters must always be set to 2'b00. 

Currently, the parameter settings are the same for x8, x16, and x4 which causes the lower DQ pins to always calibrate to the upper DQS pair instead of the DQS within its nibble. 

This requires a manual rtl modification which is outlined in this answer record.


To work around this issue, open the "rtl\ip_top\core_name_mig.sv" module and locate the assignment of the EN_OTHER_PCLK and EN_OTHER_NCLK parameters:

    parameter [2*BYTES-1:0]  EN_OTHER_PCLK      = {{2{2'b01}}, {2{2'b00}}} ,
    parameter [2*BYTES-1:0]  EN_OTHER_NCLK      = {{2{2'b01}}, {2{2'b00}}} ,

Modify these parameters to always use 2'b00 and therefore have each nibbles DQ pins calibrate to the DQS pins within the nibble:

    parameter [2*BYTES-1:0]  EN_OTHER_PCLK      = {{2{2'b00}}, {2{2'b00}}} ,
    parameter [2*BYTES-1:0]  EN_OTHER_NCLK      = {{2{2'b00}}, {2{2'b00}}} ,

Revision History:
10/21/14 - Initial Release

AR# 62551
Date Created 10/20/2014
Last Updated 10/23/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale