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AR# 62568

MIG UltraScale DDR3/DDR4 - How are the app_wdf_end and app_rd_data_end signals used?

Description

(PG150) states that the user interface signals app_wdf_end and app_rd_data_end are used to indicate that the current clock cycle is the last cycle of data on the corresponding app_wdf_data or app_rd_data bus. 

With a 2:1 (1/2 rate) controller to PHY clock ratio each Burst Length 8 (BL8) command requires two data words sent over two clock cycles with the corresponding *_end signal asserted on the second clock cycle to indicate the last cycle of data. 

However, MIG UltraScale only supports a 4:1 (1/4 rate) controller to PHY clock ratio which means for each BL8 command all of the data is sent on one cycle and the *_end signal is always asserted with the data and no longer relevant.

Solution

While the *_end signals are no longer relevant, the MIG UltraScale controller still requires that app_wdf_end is driven high along with app_wdf_wren to properly load the write data FIFO.

However, to simplify the user logic, app_wdf_end and app_wdf_wren can be tied together to ensure that they are always driven together.

App_rd_data_end is no longer needed for user logic detection of the end of the read data.

All of this information will be updated in (PG150) in a future software release.

Revision History
10/27/2014 - Initial release
AR# 62568
Date Created 10/21/2014
Last Updated 01/07/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale