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AR# 62668

UltraScale FPGA Gen3 Integrated Block for PCI Express v3.1 - Example design simulation and synthesis may fail for the VHDL version of the core

Description

Version Found: v3.1
Version Resolved and other Known Issues: See
(Xilinx Answer 57945)

When simulating and synthesizing certain configurations of the UltraScale FPGA Gen3 Integrated Block for PCI Express v3.1 core example design, if VHDL is selected as the language in the core configuration GUI, it may fail due to syntax issues.

Solution

This is a known issue to be fixed in the next release of the core. 

The following code changes are needed to work-around this issue:

In the source file pcie3_ultrascale_0.vhd <project_name/pcie3_ultrascale_0_example/pcie3_ultrascale_0.srcs/sources_1/ip/>,  make the following changes:

    • cfg_per_function_output_request => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),    -to-      cfg_per_function_output_request => '0',
    • cfg_power_state_change_ack => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),         -to-      cfg_power_state_change_ack => '0',
    • cfg_err_cor_in =>STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),                                  -to-      cfg_err_cor_in => '0',
    • cfg_err_uncor_in =>STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),                              -to-      cfg_err_uncor_in => '0',
    • cfg_config_space_enable  =>STD_LOGIC_VECTOR(TO_UNSIGNED(1,1)),                 -to-      cfg_config_space_enable => '1'
    • cfg_req_pm_transition_l23_ready => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),   -to-     cfg_per_function_output_request => '0',
In the source file pcie3_uscale_rp_top.v <project_name/pcie3_ultrascale_0_example/pcie3_ultrascale_0.srcs/sim_1/imports/simulation/dsport/>,  add the following lines:

  • At line 125         
    • wire [5:0] cfg_ltssm_state,
  • After line 781
    • .cfg_ltssm_state (cfg_ltssm_state)

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
11/14/2014 - Initial Release


AR# 62668
Date Created 10/31/2014
Last Updated 11/26/2014
Status Active
Type Known Issues
Devices
  • Virtex UltraScale
  • Kintex UltraScale
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)