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AR# 62795

Vivado 2014.3 and later - BRAM and FIFO UNIFAST models have been removed


In Vivado 2014.3 and later releases, BRAM and FIFO models are not included in the UNIFAST simulation library:



A number of issues have been reported with UNIFAST BRAM and FIFO models when they are involved in GT based design. 

The limitation of features supported in fast BRAM/FIFO models versus the full models can make it difficult to take advantage of the simulation run time speed-up for GT.

One example is where the PCIe IP Example Design is using RAMB36E1 in a mode that is not supported by the fast model.

CLKARDCLK and CLKBWRCLK of RAMB36E1 are driven by a synchronous clock.

There is no sync clocks/collision support in the UNIFAST library for RAMB36E1. 

Therefore if "-L unifast" is enabled, simulation fails with a time out error.

Because BRAM and FIFO UNIFAST models are rarely used and the runtime gain is less than 50% on these models, they have been removed from the list of UNIFAST models.

Please refer to each release of (UG900) Vivado Design Suite User Guide: Logic Simulation for a list of UNIFAST library models and their feature differences from the full models.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64053 Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries - UNIFAST N/A N/A
AR# 62795
Date Created 11/11/2014
Last Updated 05/22/2015
Status Active
Type Known Issues
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2015.1