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AR# 62881

Why does the Vivado synthesis report not show the parameter bound information in my design?

Description

Some designs show the parameter bound information:

INFO: [Synth 8-638] synthesizing module 'mig_7series_v2_1_ddr_of_pre_fifo__parameterized0' [mig_7series_0_example/mig_7series_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_1_ddr_of_pre_fifo.v:76]

      Parameter TCQ bound to: 25 - type: integer

      Parameter DEPTH bound to: 8 - type: integer

      Parameter WIDTH bound to: 6 - type: integer

      Parameter PTR_BITS bound to: 3 - type: integer

      Parameter ALMOST_FULL_VALUE bound to: 3 - type: integer

INFO: [Synth 8-256] done synthesizing module 'mig_7series_v2_1_ddr_of_pre_fifo__parameterized0' (34#1) [mig_7series_0_example/mig_7series_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/phy/mig_7series_v2_1_ddr_of_pre_fifo.v:76]


While some designs with the same code do not:

INFO: [Synth 8-638] synthesizing module 'mig_7series_v2_1_ddr_of_pre_fifo__parameterized0' [verbose/p200_9232_nt40e3_4_top.srcs/sources_1/ddr3_ctrl_1x64/user_design/rtl/phy/mig_7series_v2_1_ddr_of_pre_fifo.v:76]

INFO: [Synth 8-256] done synthesizing module 'mig_7series_v2_1_ddr_of_pre_fifo__parameterized0' (118#1) [verbose/p200_9232_nt40e3_4_top.srcs/sources_1/ddr3_ctrl_1x64/user_design/rtl/phy/mig_7series_v2_1_ddr_of_pre_fifo.v:76]


Why is the parameter bound information not always shown?


Solution

If a design contains encrypted IP cores, synthesis will not show any parameter bound information.

If you want to see the parameter bound values for a design with encrypted modules, a work-around is to make the encrypted modules out-of-context.

AR# 62881
Date Created 11/19/2014
Last Updated 02/17/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite