We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63360

Zynq - 7000 - Example of configuring an ARM MMU L2 page table


This is a simple example to configure the Zynq MMU L2 page table.
It configures the first 1M memory space (0x00000000~0x000fffff) with the L2 page table defined.
The first 192K are set inner cacheable and outer uncacheable. (As the default set for the high mapping OCM in translation_table.s)
The other parts of this 1M memory space are configured as Fault (non-accessible).
It is tested on a ZC706 with XMD command.


Please check the attachment to get the example design.
To get more information about the MMU configuration, please refer to:
Section 3.2.5 Memory Management Unit (MMU) of the Xilinx Zynq TRM (UG585) or the ARM Architecture Reference Manual (DDI0406C).


Associated Attachments

Name File Size File Type
main.c 5 KB C
zc706_tlb_l2_test_v2014_4_2015_1_21.zip 2 MB ZIP
AR# 63360
Date Created 01/20/2015
Last Updated 03/13/2015
Status Active
Type General Article
  • Zynq-7000