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AR# 63605

2015.1 SDK: How to Create an MCS Boot Image using SPI SREC BootLoader


I am using a 7 series device and want to boot from a serial flash device using an MCS image.

How can I create the boot image?


Below is the procedure to boot a 'Peripheral Test' application from a serial flash using the SPI SREC bootloader based MCS image. 

  1. Create an SPI SREC bootloader application from SDK.
  2. In SREC bootloader application sources, change the address in blconfig.h:
    #define FLASH_IMAGE_BASEADDR  <offset of the SREC image to be programmed to flash>
    For example, if the flash base address in the Vivado project (check the address editor) is 0xC2000000 and you want to give an offset of 0x00C00000 then the value of FLASH_IMAGE_BASEADDR will be 0x00C00000
  3. Change the BSP settings Include the xilisf (Xilinx In-system and Serial Flash Library)
  4. Rebuild the application.
  5. Now create one more application, for example Peripheral Test from SDK - link to DDR (in the linker script make sure that this application is executing from DDR)
  6. Convert the generated Peripheral Test elf into SREC format (mb-objcopy -O srec <elf> <srec>)
  7. Convert the Peripheral SREC file to MCS format, using write_cfgmem in Vivado (offset of the SREC file in MCS should be the offset specified in the blconfig.h)
    For the above case where FLASH_IMAGE_BASEADDR is 0xC2C00000, the command to create peripheral_test.mcs file would be:
    write_cfgmem -format mcs -size 128 -checksum FF -interface spix4 -loaddata "up 0x00C00000 /path/to/peripheral_test.srec" -force peripheral_test
  8. Use Vivado to program the peripheral_test.mcs file onto the flash
    (Note: In 2015.1 SDK, You can create the MCS files from bootgen and SDK also supports programming SPI flashes as well --> Still in test phase)
  9. Use SDK to create a download.bit from system.bit by using Program FPGA
  10. Select Bitstream (system.bit) and the ELF file to initialize BRAM (srec bootloader elf built in step 5)
  11. Program the FPGA
  12. Once the FPGA is configured, the SREC bootloader runs, copies the image from flash to DDR, and executes Peripheral Test application.

Note: In step 8, you can also add the download.bit (that would be created in step 11) to create a monolithic mcs image that will configure the FPGA as well as load the user application. 

write_cfgmem -format mcs -size 128 -checksum FF -interface spix4 -loaddata "up 0x0 /path/to/download.bit up 0x00C00000 /path/to/peripheral_test.srec" -force peripheral_test

Also, do not forget to select the appropriate value for serial_flash_family  (based on the type of serial flash you have) and serial_flash_interface in the BSP settings of the SPI SREC Bootloader:

AR# 63605
Date 04/30/2015
Status Active
Type General Article
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