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AR# 64011

Zynq-7000 AP SoC: QSPI reset example when using larger than 16MB flash


For a full description of the requirements, see (Xilinx Answer 57744) Design Advisory for Zynq-7000 SoC - Zynq and QSPI reset requirements when using larger than 16MB flash.

This Answer provide a quick example at a high level view to guide you through implementation.

Note: This example is NOT the only way to implement the "reset requirements". 

In this particular example, minor modifications to the Xilinx FSBL are required to drive the USER_IO signal (see below).


Here an example of reset flow that meets the requirements described in (Xilinx Answer 57744) Design Advisory for Zynq-7000 SoC - Zynq and QSPI reset requirements when using larger than 16MB flash.

1. At power-up, Zynq is held under reset by POR_ZYNQ driven by the CPLD
USER_IO is 3-stated therefore pulled up externally by the resistor.

2. The CPLD then de-asserts POR_ZYNQ and Zynq boots starting FSBL execution.
3. FSBL (in one of the hook functions) configures the USER_IO pin as GPO (output) and drives it to LOW (0).
In one of the hook functions (for example FsblHookBeforeHandoff() in fsbl_hooks.c) add the following:
XGpioPs_Config *ConfigPtrPS;
ConfigPtrPS = XGpioPs_LookupConfig(0);
XGpioPs_CfgInitialize(&mio_10, ConfigPtrPS, ConfigPtrPS->BaseAddr);
XGpioPs_SetDirectionPin(&mio_10, MIO_10, 1);
XGpioPs_SetOutputEnablePin(&mio_10, MIO_10, 1);
XGpioPs_WritePin(&mio_10, MIO_10, 0x0);
4. The CPLD checks (after a timeout depending on system design) if USER_IO went LOW after de-asserting the reset to Zynq.
  • If USER_IO is LOW, Zynq boot can be considered successful
  • If USER_IO is HIGH, the CPLD can react to the Zynq booting failure (For example by trying to toggle POR_ZYNQ)
5. During normal operation, if any warm reset occurs (standard code: no need to be customized) Zynq will automatically 3-state USER_IO and the signal will go HIGH.
  • The CPLD must react to USER_IO going from LOW to HIGH and reset the QSPI so that the flash is back and available before BootROM tries to access it again (3.2ms).
  • If 3.2 ms is not enough time for the QSPI to come back, the CPLD can assert POR_ZYNQ until the QSPI is ready and then de-assert it.

AR# 64011
Date Created 03/23/2015
Last Updated 04/08/2015
Status Active
Type General Article
  • Zynq-7000