When using custom attribute in RTL, Vivado Synthesis sometimes attaches the attribute to cells, and other times to nets.
What is the propagation rule for custom attribute?
A Custom attribute can be set in the following ways for Verilog and VHDL.
When the synthesis tool encounters this type of coding, it will assign that custom attribute to the driver of that signal, and if that driver still exists after synthesis is done, will attach the custom attribute to the driving cell.
However, this will not prevent the driver from being optimized if synthesis thinks it can optimize it.