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AR# 64033

2015.1 Vivado Synthesis: ERROR: [Synth 8-5548] Non zero range declaration for RAM (mem_reg) not supported. Use 0 for MSB or LSB for RAM declaration

Description

Starting in 2015.1, Vivado Synthesis will error out for memory configurations which are byte-write and have non-zero range declaration of data widths.

ERROR: [Synth 8-5548] Non zero range declaration for RAM (mem_reg) not supported. Use 0 for MSB or LSB for RAM declaration.


In the below example, memory has been declared as 8-bit wide but has used non-zero for both LSB and MSB i.e. [15:8]

module test (DO, ADDR, DI, CLK, WE);

    output reg [7:0] DO;

    input       CLK;
    input [1:0] WE;
    input [9:0] ADDR;
    input [7:0] DI;

    reg [15:8] mem [0:1023];

    always @(posedge CLK) begin
       if (WE[0])begin
           mem[ADDR][11:8] <= DI[3:0];
       end
       if (WE[1])begin
           mem[ADDR][15:12] <= DI[7:4];
       end
       DO <= mem[ADDR];
    end
endmodule

Solution

To make the above example code work, you will need to change the memory width declaration from [15:8] to [7:0] and use this replacement in each case where the original was used.

The modified code will be as follows:
 
module test (DO, ADDR, DI, CLK, WE);

    output reg [7:0] DO;

    input       CLK;
    input [1:0] WE;
    input [9:0] ADDR;
    input [7:0] DI;

    reg [7:0] mem [0:1023];

    always @(posedge CLK) begin
       if (WE[0])begin
           mem[ADDR][3:0] <= DI[3:0];
       end
       if (WE[1])begin
           mem[ADDR][7:4] <= DI[7:4];
       end
       DO <= mem[ADDR];
    end
endmodule
AR# 64033
Date Created 03/24/2015
Last Updated 04/30/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.1