The UNISIM library is used in functional simulation and behavioral simulation when the RTL instantiates device primitives.
VHDL UNISIM Library
The VHDL UNISIM library is located at <Vivado_Install_Dir>/data/vhdl/src/unisims.
It is divided into the following files, which specify the primitives for the Xilinx device families:
- The component declarations (unisim_VCOMP.vhdp)
- Package files (unisim_VPKG.vhd)
To use these primitives, place the following two lines at the beginning of each file:
You must also compile the library and map the library to the simulator.
The method depends on the simulator.
Verilog UNISIM Library
The Verilog UNISIM library is located at <Vivado_Install_Dir>/data/verilog/src/unisims.
In Verilog, the individual library modules are specified in separate HDL files.
This allows the -y library specification switch to search the specified directory for all components and automatically expand the library.
The Verilog UNISIM library does not have to be specified in the HDL file prior to using the module.
Verilog is case-sensitive, so ensure that UNISIM primitive instantiations adhere to an uppercase naming convention, for example, BUFG.
If you use precompiled libraries, use the correct simulator command-line switch to point to the precompiled libraries.
The following is an example for the Vivado simulator: