The SIMPRIM library is used for simulating timing simulation netlists produced after synthesis or implementation.
Note: Timing simulation is supported in Verilog only.
There is no VHDL version of the SIMPRIM library.
Verilog SIMPRIM Library
The Verilog SIMPRIMS library uses the same source as UNISIM with the addition of specify blocks for timing annotation.
The Verilog UNISIM library is located at <Vivado_Install_Dir>/data/verilog/src/unisims.
SIMPRIMS_VER is the logical library name to which the Verilog physical SIMPRIM is mapped.
To specify the Verilog SIMPRIM library, use the correct simulator command-line switch to point to the precompiled libraries, for example:
If you are a VHDL user, you can either run post synthesis and post implementation functional simulation (in which case no standard default format (SDF) annotation is required and the simulation netlist uses the UNISIM library), or run timing simulation by writing out a Verilog simulation netlist from the design.