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AR# 64388

7 Series MIG - DDR3 - Simulation errors when running standalone xsim_run.bat script


Version Found: MIG 7 Series v2.2

Version Resolved: See (Xilinx Answer 54025)

When running the xsim_run.bat script for an AXI DDR3 example design, the following error is received:

ERROR: [XSIM 43-4099] "C:/working/mig_calib/mig_7series_0_example/mig_7series_0_example.srcs/sources_1/imports/rtl/traffic_gen/mig_7series_v2_3_axi4_tg.v" Line 69.
Module mig_7series_v2_3_axi4_tg(C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=28,C_AXI_DATA_WIDTH=64,C_AXI_NBURST_SUPPORT=0,C_EN_WRAP_TRANS=0,C_BEGIN_ADDRESS=32'b0,C_END_ADDRESS=32'b0111111111111,PRBS_EADDR_MASK_POS=32'b11111111000000000000000000000000,DBG_WR_STS_WIDTH=40,DBG_RD_STS_WIDTH=40,ENFORCE_RD_WR=0,ENFORCE_RD_WR_CMD=8'b010001,EN_UPSIZER=0,ENFORCE_RD_WR_PATTERN=3'b0) doesn't have a timescale but at least one module in design has a timescale.


This error occurs because "`timescale 1ps/1ps" exists in the _cmd_prbs_gen_axi.v module only, and not in any of the other AXI TG files.

Adding the timescale definiton to all the AXI TG files resolves the issue.

The error message is not received when launching XSIM through the Vivado GUI.

This is because the "-relax" switch is used during elaboration by default, which reduces this error message to a warning.

An alternative workaround would be to add "-relax" to the xelab command in xsim_run.bat.

Revision History:

04/27/2014: Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 64388
Date 06/15/2015
Status Active
Type General Article
  • MIG 7 Series
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