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AR# 64735

Vivado 2015.1 - Debug core is being generated with unconnected clock


For certain designs In Vivado 2015.1, (Particularly those involving MIG) using the "Setup Debug" wizard to create a debug core leave the clk port unconnected and results in the following Critical Warning:

CRITICAL WARNING: [Chipscope 16-3] Cannot debug net 'u_mig_0/inst/u_rld3_mem_intfc/u_mig_rld3_phy/inst/u_rld3_infrastructure/c0_rld3_ui_clk'; it is inside a ChipScope core.

Implementation Fails due to this missing CLK.


This is a known issue in Vivado 2015.1, as it blocks debugging of signals inside ChipScope cores.

To work around this issue, do one of the following:

1. After the Set Up Debug step is completed and when the Critical Warning is seen, manually add the clock using the following Tcl command:

connect_debug_port u_ila_0/clk [get_nets [list c0_rld3_ui_clk ]]

2. Alternatively, use this set_param before the Setup Debug step:

set_param chipscope.forbidDebugCS false

This issue is fixed in Vivado 2015.2.

AR# 64735
Date 07/15/2015
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2015.1
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