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AR# 64809

2015.1/2 - Vivado Simulator Tactical Patch - ERROR: [XSIM 43-3316] Signal SIGSEGV received when GTHE2 is called in mixed language design


When simulating my design with Vivado Simulator, I get the following error:

Compiling module srio_gen2_v3_3.srio_gen2_v3_3_phy_top(TCQ=100,S...
Compiling architecture xilinx of entity srio_gen2_v3_3.srio_gen2_v3_3_phy [\srio_gen2_v3_3_phy(0,1,6,0,1,1,...]
Compiling architecture imp of entity srio_gen2_v3_3.srio_gen2_v3_3_unifiedtop [\srio_gen2_v3_3_unifiedtop("srio...]
Compiling secureip modules ...
ERROR: [XSIM 43-3316] Signal SIGSEGV received.

The same design can pass simulation in Questa.


This crash can occur when a GT cell is called in both VHDL and Verilog modules in a mixed-language design.

Note: GTXE2, GTPE2, GTHE2 and their fast varieties all have the same problem. Only GTXE2 and GTPE2 models are fixed in 2015.3 and beyond.

At the end of this answer record are links to the 2015.1 and 2015.2 patches.

To use this new SecureIP library, please remove the $XILINX_VIVADO/data/xsim/verilog/secureip directory from your build, unzip and untar the secureip.tar.gz file and copy the resulting secureip directory to $XILINX_VIVADO/data/xsim/verilog.

For GTHE2, if you need a patch for 2015.3 or 2015.4, please open a service request with Xilinx Technical Support.

2015.1 patch:


2015.2 patch:


AR# 64809
Date Created 06/16/2015
Last Updated 12/09/2015
Status Active
Type Known Issues
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.4