When simulating my design with Vivado Simulator, I get the following error:
The same design can pass simulation in Questa.
This crash can occur when a GT cell is called in both VHDL and Verilog modules in a mixed-language design.
Note: GTXE2, GTPE2, GTHE2 and their fast varieties all have the same problem. Only GTXE2 and GTPE2 models are fixed in 2015.3 and beyond.
At the end of this answer record are links to the 2015.1 and 2015.2 patches.
To use this new SecureIP library, please remove the $XILINX_VIVADO/data/xsim/verilog/secureip directory from your build, unzip and untar the secureip.tar.gz file and copy the resulting secureip directory to $XILINX_VIVADO/data/xsim/verilog.
For GTHE2, if you need a patch for 2015.3 or 2015.4, please open a service request with Xilinx Technical Support.