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AR# 64869

Kintex UltraScale FPGA KCU105 Evaluation Kit - ETH PHY link issues


If issues are seen with the Ethernet PHY not linking up on the Kintex UltraScale FPGA KCU105 Evaluation kit, what steps can be taken?


If the Ethernet PHY is not linking up on the KCU105 Evaluation Kit, the Si570 clock input frequency should be checked. 

This clock frequency should be 156.25 MHz.

This clock can be programmed via the System Controller Clock Menu.

The Clock Menu can be accessed from the Main KCU105 System Controller menu:

For the Clock menu select option 1.

More information on the System Controller can be found in (UG917), the KCU105 User Guide.


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AR# 64869
Date Created 06/26/2015
Last Updated 07/02/2015
Status Active
Type General Article
Boards & Kits
  • Kintex UltraScale FPGA KCU105 Evaluation Kit