(UG810) KC705 Evaluation Board User Guide (v1.6.1) lists the Clock Source to FPGA U1 Connections in Table 1-9.
What is the correct I/O Standard for SYSCLK_N and SYSCLK_P?
SYSCLK_N and SYSCLK_P connect to U1 FPGA Pins AD11 and AD12 respectively.
AD11 and AD12 are in Bank 33 of the XC7K325T device.
Bank 33 is a HP I/O Bank.
The LVDS I/O standard is only available in the HP I/O banks and requires a VCCO of 1.8V.
The I/O Standard in Table 1-9 for SYSCLK_N and SYSCLK_P should be LVDS, not LVDS_25.
Table 1-9 is updated in UG810 v1.6.2:
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