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AR# 65169

2015.2 - AXI QUAD IP Core - What to do with ss_i(x) signals in Slave mode core configuration settings.

Description

When configuring an AXI QUAD IP Core in Slave mode, I can still see SS_i(x) signals are being generated.

Why does this occur?

Solution

This occurs because the Core has an SS_i input port which is unused in the design. 

In this case you should tie it to 0.


AR# 65169
Date Created 08/10/2015
Last Updated 10/06/2015
Status Active
Type General Article
Devices
  • SoC
  • FPGA Device Families
Tools
  • EDK
  • ISE Design Suite
  • Vivado Design Suite
IP
  • AXI Serial Peripheral Interface