We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65224

2015.1/2 - AXI Quad SPI - V3.2 and below - Why do I see extra clocks at the end of the transfer of SPI legacy mode (SPIx1)


When using AXI Quad SPI in Standard Master Mode (SPIx1) without FIFO, I am seeing the following behavior:

  • Extra SCK clock pulses
  • SCK clock is running continuously
  • DRR overrun bit in the status register does not clear


Work-around: Enabling FIFO, or (if possible) reducing AXI and SPI clock ratio, or both can help in most cases.

The RTL is fixed in the Vivado 2015.3 release for this issue.

AR# 65224
Date 09/11/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7Q
  • Kintex UltraScale
  • More
  • Virtex UltraScale
  • Virtex-7
  • Virtex-7Q
  • Less
  • Vivado Design Suite
  • AXI Serial Peripheral Interface
Page Bookmarked