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AR# 65459

Power - Mitigating the Effects of Power System Resonance.


Are there any documents related to Power System Resonance?

How do I identify and mitigate noise generated from my FPGA design?


Power rail resonance is an inherent characteristic of all semiconductor devices due to die/package resistance, capacitance and inductance.

Every power rail will resonate at a frequency determined by those parameters. Optimal system design avoids operation at or near the resonant frequencies, to reduce AC swings on the power supply distribution network.

Effects of Resonance

When a circuit operates at its resonant frequency, the impedance is at its maximum, which limits the amount of current that the circuits load can accept.

In the case of an FPGA, where the circuit is a combination of thousands, or millions, of logic elements, being starved for current can cause voltage levels to drop below specification which can lead to:

  • Problems with jitter that can result in clocking problems

  • Increased logic delays that can hinder timing

  • Functional failure

Operating at or near resonance can also make a circuit especially sensitive to any increase in loading.

An increase in loading will lead to an increase in current consumption, which will starve the circuit even more for current, putting more strain on the supply voltage, which will further exacerbate jitter and timing margins.

Figure 1 shows an example plot of VCCINT resonant frequencies over several 7 Series FPGAs. At the resonant frequency, the impedance of the die circuitry is at its maximum.

Operating at resonance provides the least amount of margin in order to keep the power rail within specification. It is recommended to minimize operation at the resonant frequency plus or minus 20% to ensure optimal performance.

Figure 1: Example Resonant VCCINT frequencies

7 series devices have a range of resonant frequencies (across all die/package combinations) of ~20 to 85MHz. Specific resonant frequency data can be requested directly from Xilinx, as required.

Operating large amounts of logic (>50% of the device) at high toggle rates (>25%) at the devices specific resonant frequency (+/- 20%) should be avoided.

If it is not possible to avoid operation at the devices specific resonant frequency (+/-20%), the following methods can be used to mitigate the effects of resonance:

Mitigating the Effects of Resonance

The best way to avoid resonant frequency operation is to plan around it during the initial planning stages of the design. After the initial design stage, there are still other steps that can be taken to reduce the effects of resonance.

Optimize clock topologies:

Keeping paths short and close reduces delays that are exacerbated by operation at resonance (jitter, timing margins).

For best results:

  • The MMCM or PLL must be in the same bank as the input for a direct connection from the input buffer
  • MMCM and PLLs should not be cascaded
  • BUFGs should not be cascaded

Split Clock Domains into Multiple Phases:

Refer to Figure 2 and the following example to illustrate how this works:

Example: Put approximately half of the aggressor Logic, BRAM, and DSP at 0 and half at 180.

  • Drops the number of simultaneous switching events by 50%
  • Scales the effective switching rate by a 2x increase in frequency
  • Higher frequency switching hits the impedance curve at lower impedance
  • This is a double benefit
    • Impedance drops from m0 at f1=77.76 MHz to m2 at 2*f1=155.52 MHz
    • Number of switching elements drops by 50%

Figure 2: Mitigating Resonance by splitting clocks into multiple phases


Knowledge of resonant frequencies and designing around and/or mitigating their effects can help to ensure a robust, functional, and ultimately successful design.

AR# 65459
Date Created 09/21/2015
Last Updated 09/22/2015
Status Active
Type General Article
  • FPGA Device Families