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AR# 65506

MIG UltraScale - DDR4/DDR3 - Read data errors may be seen if memory accesses do not occur on the 0x8 address boundary


Version Found: MIG UltraScale v7.1

Version Resolved: See (Xilinx Answer 58435)

MIG UltraScale DDR4/DDR3 IP does not support SDRAM burst ordering, and as a result the controller ignores the three LSBs of app_addr. 

The following is from PG150:

"Note that the three LSBs of app_addr map to the column address LSBs which correspond to SDRAM burst ordering. The controller does not support burst ordering so these low order bits are ignored, making the effective minimum app_addr step size hex 8.."

However, the memory controller only ignores app_addr[1:0], and app_addr[2] is passed through to the column address sent on the PHY interface.

If users send a read command that is not on the even 0x8 boundary, then burst ordering might unknowingly occur and the read data will be returned out of order, triggering data errors.


As stated in PG150, the effective minimum app_addr step size in UltraScale is 0x8.

If you design your logic to only access memory locations on an even 0x8 boundary, then no issues will be seen.

App_addr[2] will be correctly ignored in a future release of the IP.

Revision History:

11/11/2015 - Initial Release

AR# 65506
Date 11/18/2015
Status Active
Type Known Issues
  • MIG UltraScale
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