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AR# 65733

DDR4/3 UltraScale - 72-bit designs with ECC enabled, may fail during calibration due to improper data mask (DM) connection on the PCB


The DDR4/3 UltraScale memory IP requires 72-bit data width design with ECC enabled to not use Data Mask (DM). 

As per PG150:

"Data Mask (DM) option is always selected for AXI designs and is grayed out (you cannot select it). For AXI interfaces, Read Modify Write (RMW) is supported and for RMW to mask certain bytes of Data Mask bits should be present. Therefore, the DM is always enabled for AXI interface designs.

This is the case for all data widths except 72-bit. For 72-bit interfaces, ECC is enabled and DM is deselected and grayed out for 72-bit designs. If DM is enabled for 72-bit designs, computing ECC does is not compatible, so DM is disabled for 72-bit designs."

Failure to properly tie DM low on the PCB will result in calibration failures similar to the following:

CAL_STATUS.RANK0.10_WRITE_DQS_TO_DQ(SIMPLE)                   string  true       FAIL


To ensure successful calibration with the DDR4/3 Memory IP, please refer to the memory vendor for specifics on the DM pull-down when the pin is not use.

AR# 65733
Date Created 10/18/2015
Last Updated 11/04/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale