Version Found: 2015.3
The High Speed I/O Wizard pin selection is organized starting at Byte 0, Pin 0 at the top of the interface.
This is different to how the I/Os are placed within the FPGA which could cause confusion for the placement of the Bitslices.
Note: this Answer Record should not be viewed in isolation, for all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
This issue is resolved in version 3.0 of the High Speed SelectIO Wizard, included in the 2016.1 release.
In older versions, because the SelectIO logic associated with the high speed interfaces (For example, RXTX_BITSLICE and BITSLICE_CONTROL) will depend on the placement, this ordering can cause confusion.
Within the FPGA the blocks are ordered from the bottom of the device as shown in (UG571), but in the High Speed SelectIO Wizard Interface, the Pin Selection interface has been annotated to identify the lower and upper nibbles associated with Byte Group 0.
Additionally notice how the lower nibble contains 6 Bitslices while the upper nibble contains 7, it should be noted that Bitslice 6 in the upper nibble is single ended only.
This will additionally be important if strobes are required, as strobes will be available in the pin0 or pin6 for each of the bytes.
The diagram below shows the differences in implementation between the User Guide and the HSSIO Wizard for Byte Group 0.