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AR# 66183

Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the Zynq UltraScale+ MPSoC Processing System IP and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History


Zynq UltraScale+ MPSoC Processing System IP Page:

http://www.xilinx.com/products/intellectual-property/zynq-ultra-ps-e.html

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
Initial Release2015.2
1.02015.2.1
1.0 (Rev 1)2015.3
1.0 (Rev 2) 2015.4
1.12016.1
1.22016.2
2.02016.3


General Guidance

The table below provides answer records for general guidance when using the Zynq UltraScale+ MPSoC IP.

Answer RecordTitle
(Xilinx Answer 55248)Vivado Timing and IP Constraints
(Xilinx Answer 65467)Zynq UltraScale+ MPSoC - Boot and Configuration
(Xilinx Answer 64375)Xilinx UltraScale+ MPSoC Solution Center
TBD
Zynq UltraScale+ MPSoC - Silicon Revision Differences
(Xilinx Answer 66071)Design Advisory for Zynq UltraScale+ MPSoC Devices


Known and Resolved Issues

The following table provides known issues for the Zynq UltraScale+ MPSoC, starting with v1.0 (Rev 2), released in the Vivado 2015.4 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion
Found
Version
Resolved
(Xilinx Answer 67861)Design Advisory for Zynq UltraScale+ MPSoC Processing System - How do I upgrade from Vivado 2016.2 and earlier?
2016.3N/A
(Xilinx Answer 68184)
PS LPDDR4 devices do not complete psu_init initialization 2016.3
(Xilinx Answer 65982) Zynq UltraScale+ MPSoC, Vivado 2015.4 - Patch for PS DDR3/DDR4/LPDDR4 and GTR transceiver support2015.42016.1
(Xilinx Answer 66218)Zynq UltraScale+ MPSoC - psu_init flow is not working due to difference between psu_int.c and psu_init.tcl2015.42016.1
(Xilinx Answer 66219)Zynq UltraScale+ MPSoC - Bringing Processors out of reset by configuring the Processor Block level software controlled reset registers in JTAG mode2015.42016.1
(Xilinx Answer 66295)Zynq UltraScale+ MPSoC - PS-PL AXI Interfaces do not function correctly at 64- or 32-bit widths (or 128-bits for M_AXI_HP0_LPD) 2015.42016.3
(Xilinx Answer 66220)Zynq UltraScale+ MPSoC - Reset Signal Availability for PS+PL designs 2015.42016.1
(Xilinx Answer 66223)Zynq UltraScale+ MPSoC - DRC with default configuration for DDR2015.42016.1
(Xilinx Answer 66224)Zynq UltraScale+ MPSoC - Zynq UltraScale+ MPSoC wrapper throws syntax error when project is set to VHDL - for PS-only design2015.42016.1
(Xilinx Answer 66225) Zynq UltraScale+ MPSoC - Limitations with hand-off to software (SDK) when we have segments created in memory to be accessible from a specific master2015.42016.1
(Xilinx Answer 66226) Zynq UltraScale+ MPSoC - Failure while creating an application for MicroBlaze with PS DDR as code execution memory2015.42016.1
(Xilinx Answer 66227) Zynq UltraScale+ MPSoC - Use of Split clock with slave interface2015.42016.1
(Xilinx Answer 66247)Zynq UltraScale+ MPSoC - Slightly different PS power numbers reported between Windows and Linux hosts2015.42016.1
(Xilinx Answer 66045)Zynq UltraScale+ MPSoC - How do I connect the UART MODEM signal to EMIO while using MIO?2015.42016.1
(Xilinx Answer 66571)Zynq UltraScale+ MPSoC - Processor System IP GUI Limitations with PS DDR topologies2015.42016.1


Revision History

12/12/2015 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64375 Xilinx Zynq UltraScale+ MPSoC Solution Center N/A N/A
63538 Vivado Design Suite 2015 - Known Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
55248 Vivado Timing and IP Constraints - Why do I get the following CRITICAL WARNING: [Vivado 12-259] No clocks specified,​ please specify clocks, for my IP, or why do I get CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_max_delay? N/A N/A
65467 Zynq UltraScale+ MPSoC - Boot and Configuration N/A N/A
64375 Xilinx Zynq UltraScale+ MPSoC Solution Center N/A N/A
66071 Design Advisory Master Answer Record for Zynq UltraScale+ MPSoC Devices N/A N/A
66218 Zynq UltraScale+ MPSoC Processing System IP - psu_init flow is not working due to differences between psu_int.c and psu_init.tcl N/A N/A
66219 Zynq Ultrascale+ MPSoC Processing System IP - Bringing Processors out of reset by configuring the Processor Block level software controlled reset registers in JTAG mode N/A N/A
66220 Zynq UltraScale+ MPSoC Processing System IP - Reset Signal Availability for PS+PL designs N/A N/A
66224 Zynq UltraScale+ MPSoC Processing System IP - Zynq UltraScale+ MPSoC wrapper throws syntax error when project is set to VHDL - for PS-only design N/A N/A
66225 Zynq UltraScale+ MPSoC SDK - Limitations with hand-off to software (SDK) when we have segments created in memory to be accessible from a specific master. N/A N/A
66226 Zynq UltraScale+ MPSoC, SDK - Failure when creating an application for MicroBlaze with PS DDR as code execution memory N/A N/A
66227 Zynq UltraScale+ MPSoC Processing System IP - Use of Split clock with slave interface N/A N/A
65982 Zynq UltraScale+ MPSoC, Vivado 2015.4 - Patch for PS DDR3/DDR4/LPDDR4 and GTR transceiver support N/A N/A
66247 Zynq Ultrascale+ MPSoC Processing System IP - Slightly different PS power numbers reported between Windows and Linux hosts N/A N/A
66295 Zynq UltraScale+ MPSoC Processing System IP - PS-PL AXI Interfaces do not function correctly at 64-bit or 32-bit widths (or 128-bits for M_AXI_HP0_LPD) N/A N/A
66223 Zynq UltraScale+ MPSoC Processing System IP - Incorrect DRC with default configuration for DDR N/A N/A
66045 Zynq UltraScale+ MPSoC, Vivado 2015.4: How do I connect the UART MODEM signal to EMIO while using MIO? N/A N/A
66571 Zynq UltraScale+ MPSoC, Vivado 2015.4 - Processor System IP GUI Limitations with PS DDR topologies N/A N/A
68184 Zynq UltraScale+ MPSoC - PS LPDDR4 devices do not complete psu_init initialization N/A N/A
AR# 66183
Date Created 12/10/2015
Last Updated 11/10/2016
Status Active
Type Release Notes
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.1
  • Vivado Design Suite - 2016.3
IP
  • Zynq UltraScale+ MPSoC Processing System