We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66208

High Speed SelectIO Wizard - Example design does not check for alignment across the whole interface


Version Found: 2015.3

The example design generated by the High Speed SelectIO Wizard does not check for alignment of data between the bit slices, it only check on an individual channel basis.

Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)


To work around this issue, you can add the following comparison code at the top level of the example design or within the test bench.

The following example is a simple check to make sure pin0, pin1, pin2 and pin3 all match.

In this example pll0_clkout0 is used for driving the fifo_rd_clk_0:

    always @ (posedge pll0_clkout0)
      core_data_aligned_all = (data_to_fabric_bg0_pin0 == data_to_fabric_bg0_pin1) 
                && (data_to_fabric_bg0_pin0 == data_to_fabric_bg0_pin2)
               && (data_to_fabric_bg0_pin0 == data_to_fabric_bg0_pin3);

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 66208
Date Created 12/11/2015
Last Updated 12/18/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale