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AR# 66218

Zynq UltraScale+ MPSoC Processing System IP - psu_init flow is not working due to differences between psu_int.c and psu_init.tcl

Description

The configuration/entry to de-assert the Software controlled reset register for the LPD block, LPD IOU, and FPD Block level (afi_fm5_reset afi_fm4_reset afi_fm3_reset afi_fm2_reset afi_fm1_reset afi_fm0_reset) are not present in psu_init.tcl.

psu_int.c (fsbl) does contain these entries.

As a result, the psu_init.tcl flow does not work when these blocks are used in the design.

Example: PS-PL interface

Solution

This issue is expected to be fixed in 2016.1.

Work-arounds:

  1. Use FSBL instead of the Tcl flow
  2. Update psu_init.tcl manually using the steps below (Only Applicable for non DDR systems)
    1. Open the psu_init.tcl file in the HW Platform folder in SDK workspace, and search for the psu_init proc.
    2. Replace this with the code below:

         proc psu_init {} {
           variable psu_mio_init_data 
           variable psu_pll_init_data
           variable psu_clock_init_data
           variable psu_peripherals_init_data
           variable psu_resetin_init_data
           variable psu_resetout_init_data
           variable psu_serdes_init_data
           variable psu_resetin_init_data
           variable psu_peripherals_powerdwn_data
           variable psu_security_data
           # psu_ddr_phybringup_data
          init_ps [subst {$psu_mio_init_data $psu_pll_init_data $psu_clock_init_data }]
          init_ps [subst {$psu_peripherals_init_data $psu_resetin_init_data }]
          init_serdes
          init_ps [subst {$psu_serdes_init_data $psu_resetout_init_data }]
          init_peripheral 
          init_ps [subst {$psu_peripherals_powerdwn_data $psu_security_data }]
      }

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A
AR# 66218
Date Created 12/11/2015
Last Updated 01/12/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2015.4
IP
  • Zynq UltraScale+ MPSoC Processing System