We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 66223

Zynq UltraScale+ MPSoC Processing System IP - Incorrect DRC with default configuration for DDR


In the Processor Configuration Wizard on the DDR configuration page, if I change the type from DDR4 to DDR3 a DRC is displayed with default values.


Please refer to the DRC errors and resolve them manually as suggested.

For Example: Set the DDR clock frequency to 400 MHz from 800 MHz as it would be out of range and so on.

This is expected to be fixed in the 2016.1 release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A
AR# 66223
Date Created 12/11/2015
Last Updated 12/29/2015
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
  • Vivado Design Suite - 2015.4
  • Zynq UltraScale+ MPSoC Processing System