When the placer puts a RAM32X1D in a slice where a RAM64M is already present, the router is found to tie the address pins to VCC (instead of GND) on both RAMs.
In this particular case, the netlist showed DRAM's WA5 and WA6 pins connected to GND, as per the expected behavior. (Connection of both, WA5 and WA6 to VCC is also acceptable)
However, the post-implemented device view shows only WA6 connected to VCC. This implies that the placer is somehow swapping the t connection of WA6 from GND to VCC.
RAMD64Es affected by this issue change from run to run depending on the packing of other DRAM primitives. This causes the bitstream to be incorrect and the design to be non-functional.
This problem has been fixed for Vivado 2016.1. Meanwhile, the attached Tcl script provides a workaround by connecting both pins (WA5 and WA6) to VCC:
Results of the Tcl script were tested after applying at pre-route stage only. (PFA)
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