A Tri-Mode Ethernet MAC (TEMAC) core configured for RGMII PHY might need for the Phase on the input receive clock to be adjusted in order to meet timing, or increase the window margin.
This article provides information on how to adjust the phase of the RX input clock (RXC) in a TEMAC RGMII system.
In its default form, the core does not have the circuitry which would allow you to change the phase of the RXC inside of the FPGA.
The phase of the RXC can be easily changed by adding an IDELAY element in its path. The RX clocking circuitry is present in the HDL file named <component_name>_rgmii_v2_0_if.v[hd].
The IDELAY component, which will be used to adjust the phase of the RXC, must be instantiated in this module.
Change the parameter IDELAY_VALUE to the required value in the top level XDC.
Please see the example below, and refer to the User Guide (UG471) for more details on IDELAY attributes.