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AR# 66554

DDR4 IP - a 300MHz reference input clock cannot be chosen for 1333MHz (750ps) output clock frequency


Version Found: v1.1

Version Resolved: See (Xilinx Answer 58435)

For UltraScale+ devices only, the DDR4 IP does not allow an exact 300MHz reference input clock frequency to be chosen for a 1333MHz (750ps) output clock frequency. 

The closest available reference input clock frequency is 296.296MHz (3375ps). How can I get exactly 300MHz?


To ensure 2667Mbps operation using a 300MHz input reference clock, the following two options are available:

  1. Select a different Interface Speed and Reference Input Clock combination:
    • Select 751ps (1331MHz) for the "Memory Device Interface Speed" in the DDR4 IP GUI
    • Select 337 (299.67MHz) for the "Reference Input Clock Speed" in the DDR4 IP GUI

      Note: This configuration sets up the correct MMCM M/D values to use an exact 300MHz reference input clock to achieve exactly 2667Mbps performance.
  2. Manually override the MMCM M/D values inside the DDR4 IP source code
    • To manually make modifications to the IP source code, a custom IP Repository must be created.
    • To use the IP Repository flow, follow these steps:
      1. Copy the DDR4 Controller directory from your Vivado install area. For example:
      (Full IP) C:\Xilinx\Vivado\2015.4\data\ip\xilinx\ddr4_v1_1
      2. Make your edits to the source code in this copied directory and store the files in a location of your choice. Somewhere in your project directory is recommended.
      (Full IP) make edits to user_design_top.ttcl lines 1052 through 1060
      .CLKIN_PERIOD_MMCM (3333),
  3. You then have to add it in the IP Catalog. Click on the IP Settings:
 4. Then Add a Repository, point to the newly edited PHY directory, and Refresh All. The IPs in the repository should be displayed in the lower box.

The following screen capture is an example of what it should look like:

The IP in the standard MIG directory will now be over-ridden and you will see your edits when you generate the IP and look at the relevant code.

Revision History:

02/05/2016 - Initial Release

AR# 66554
Date Created 02/05/2016
Last Updated 02/08/2016
Status Active
Type Known Issues
  • Kintex UltraScale+
  • Virtex UltraScale+
  • MIG UltraScale