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AR# 66592

Zynq UltraScale+ MPSoC - SGMII using PS-GTR

Description

In Zynq UltraScale+ MPSoC, SGMII in PS using PS-GTR is supported.

Below is a list of questions you might have when starting to use SGMII mode with PS-GTR.

Solution


1) Is there a reference design for connecting a GE PHY to a GTR via SGMII?

No, there is no reference design for connecting a GE PHY to GTR via SGMII.


2) Is there a reference design specifically for the Marvell 88E1111?

No, the design is targeting Zynq UltraScale+.


3) Is AC coupling required between the GTR and the 88E1111? (In the KCU105 which uses this same PHY in SGMII mode it is done with DC coupling, but it is connected to SelectIO.)

AC coupling is required on TXP/TXN and RXP/RXN pins going to/from GTR to Marvell PHY.


4) Are there any other reference clock options other than 125MHz? I am not sure what the 88E1111 needs for a clock, but on the KCU105 it looks like a 25MHz crystal is used. Is there a clock that the 88E1111 generates that could be used for the GTR refclk?

The GTR reference clock should be 125 MHz.


5) What are the jitter specs for the GTR refclk when running SGMII? I want to know what quality of the reference clock is required for the GTR refclk input.

The following is per DS925 (page 48)



We have not fully characterized the phase noise mask yet. Below is the max clock phase noise:

-140 dBc/Hz from 50 kHz to 10 MHz.


6) Does the Gigabit Ethernet controller in the MPSoC use a clock from the SIOU derived from the GTR refclk? Or does it require another clock? What clock sources and frequencies can be used by the GE controller?

GEM in MPSoC does use the clocks from SIOU derived from the GTR refclk.


7) Is there anything else that can be done to reduce the number of clocks needed to make this Ethernet solution work? It seems like we might need 3 different clocks to make Ethernet on an RJ45 work?

The design requires a 25MHz clock for the 88E1111 controller. For GTR a dedicated differential input clock is required. A PS_CLK is required to operate a PS interface. As a result, three different clocks are needed.


8) Are there any special layout rules for PS_MGTRREF?


 

This pin needs to be grounded via a 500 Ohm resistor.


9) Is an MDIO interface needed between the MPSOC and the 88E1111 in addition to the SGMII data pins? If yes could you please list the possibilities? I assume this would be on MIO or EMIO?

An MDIO interface is optional. Requirement for MDIO is driven by the system level requirement which needs to be supported. 

Please consult the 88E1111 product guide for information on what can be controlled using MDIO. If any of the features that can be implemented through MDIO become a system requirement, you can implement the interface.

It can be routed to either MIO or EMIO.

For example, some settings (like changing PHY address, disabling sleep mode, controlling auto-negotiation), of the PHY can be modified using an MDIO interface if there is a need.


10) Is there a Proper initialization sequence required for the lanes when SGMII mode is used - clock, etc.

Yes, you need to follow an initialization sequence for SGMII protocols. PCW settings do not work for SGMII. Please refer to the attached SGMII initialization script for SGMII.


11) Is there a designation of master preferred/slave preferred on the interface?

There is no preference as to master or slave.


12) How do I verify a valid SGMII link has been negotiated? Are there any registers that indicate link attempt, lane quality, master/slave clock configuration, etc?

The PCS_STATUS register at offset 0x204 indicates link_status. Refer to bit [2] of this register. For register details, please refer to (UG1087).


13) What is the purpose of the PCS control registers for SGMII and description of them for SGMII mode?

You can use the PCS_CONTROL register to select speed, control Auto-negotiation, apply loopback and for PCS reset.

For SGMII mode, these bits are applicable. You can also change speed to 10/100 in SGMII mode.


14) GEM_CTRL (IOU_SLCR) Register Description

GEM3_SGMII_SD 7:6 rw 0x0

00: Tie the PCS signal detect to 0

01: Tie the PCS signal detect to 1

10: Signal detect from the external optical PHY via FMIO

11: Reserved.


Does forcing to 1 indicate signal presence?

Yes, forcing this signal to 1 indicates signal presence from the optical PHY (you can force it via this register or route the signal_detect signal from the PL).


15) How was the SGMII interface validated?

SGMII was validated using the following flow:

  1. Initialize the GTR mux and transceiver interface using the SGMIIinit.tcl file. This step needs to be done after running the default FSBL.
  2. Boot PetaLinux using the 2016.1 branch.
  3. Update the device tree to modify the phy-type to "sgmii". Here is the snippet -
 
&gem2 {
        phy-handle = <&phy0>;
        phy-mode = "sgmii";
        phy0: phy@0{
                reg = <0>;
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
        };
};


16) I have a configuration that tries to select SGMII for GTR lanes 0,1,2 using the 125mhz reference clock coming in on PS_MGTREFCLK_1P/N on the ZCU102. (from psu_init.c). What else do I need to do to make it work?

These protocol specific configurations are not an issue, but you will need to set additional registers to make it work.


  1. Make sure all lane calibration is done.
  2. Put all GEM in reset L0-L2
  3. Set the pll_ref_clk to be 125 Mhz (PLL_REF_SEL*) 
  4. Ref clock selection (L0_L*_REF_CLK_SEL_OFFSET)
  5. Set lane protocol to SGMII (ICM CFG)
  6. Set TX and RX bus width to be 10 (TX/RX_PORT_BUS_WIDTH)
  7. Bypass descrambler and 8b/10b (L*_TM_DIG_6 and L*_TX_DIG_TM_61)
  8. Take the GEM controllers out of reset
  9. Check for PLL lock (L*_PLL_STATUS_READ)

Attachments

Associated Attachments

Name File Size File Type
SGMIIInit_4lane_init.tcl 10 KB TCL
AR# 66592
Date Created 02/11/2016
Last Updated 06/23/2016
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2015.4.1
IP
  • Processing System 7