Version Found: DDR4 v2.0
Version Resolved: See (Xilinx Answer 69035)
When targeting DDP (Dual Die Package/Twin Die) DDR4 components in UltraScale+, the data width can be expanded with multiple components.
Due to the double loading inside the DDP part and Xilinx signal integrity analysis, in order to achieve 2400Mbps, the number of components needs to be limited to five.
For six or more components the frequency must be limited to 2133Mbps.
In Vivado 2016.1, this frequency and component number limit is not adhered to within the DDR4 Wizard. In addition, if an older IP version that violates the frequency requirement is brought into a newer version of Vivado, no DRC errors will occur.
You will need to manually ensure when selecting six or more components to set the frequency to 2133Mbps or less.
|08/11/2016||Updated to include message on DRC|